Top answer: A processor’s core has an L1 cache and all of the cores share an L2…

  

A processor’s core has an L1 cache and all of the cores share an L2… A processor’s core has an L1 cache and all of the cores share an L2 cache on the chip and an L3 cache off the chip, backed up by DRAM. Assume the L1 cache has a hit time of .5 ns, the L2 cache has a hit time of 1.5 ns, the L3 cache has a hit time of 5 ns and DRAM has an access time of 15 ns. The L1 cache has a hit rate of 86.6%, L2 has a hit rate of 91.4%, L3 has a hit rate of 94.9% and DRAM has a hit rate of 100%.                 a. What is the effective access time for this processor?                b. If we remove the L3 cache, what does the effective access time become?  Engineering & Technology Computer Science CSC 362